1. Field of the Invention
The present invention relates to a method of manufacturing an integrated semiconductor circuit and an integrated semiconductor circuit fabricated thereby, and more particularly, to a method for forming a metal interconnection and a contact structure fabricated thereby.
2. Description of the Related Art
In general, semiconductor devices include transistors, resistors and capacitors. Metal interconnections are required for interconnecting the semiconductor devices to complete the formation of an integrated circuit. The metal interconnections, which transmit electric signals, must have low electric resistance, and be economical and reliable. Aluminum has been widely used as a material for the metal interconnections.
As semiconductor devices become more highly integrated, the width or thickness of the metal interconnection must be reduced, requiring the size of a contact hole be reduced. As a result, the aspect ratio of the contact hole increases, requiring new methods for completely filling the contact hole with the metal interconnection. A selective chemical vapor deposition (CVD) process has been proposed as a method for completely filling the contact hole having a high aspect ratio with the metal interconnection. The selective CVD process uses the characteristic in which a growth rate of the metal layer on an insulating layer is different from that on a conductive layer.
Conventionally, an interdielectric layer formed on a semiconductor substrate is patterned to form a plurality of contact holes exposing a predetermined area of a lower interconnection interposed between the interdielectric layer and the semiconductor substrate. Then, metal plugs may be formed within the contact holes using the selective CVD process. Here, in the case where at least one of the plurality of contact holes has a depth different from that of the other contact holes, even if all the contact holes have the same diameter, it is difficult to form metal plugs level with the surface of the interdielectric layer in all of the contact holes. In other words, if a metal plug completely filling the deepest contact hole is formed, a metal plug formed within a shallow contact hole will have a protrusion having a height higher than the surface of the interdielectric layer. Therefore, it is difficult to form metal plugs without such a protrusion in a plurality of contact holes having different depths from one another using conventional selective CVD processes.
Also, as the integration density of the semiconductor device increases, the junction depth of a source/drain region of a transistor is reduced. Accordingly, an aluminum layer, used as the metal interconnection, penetrates into the shallow source/drain region, thereby causing a junction spiking phenomenon. To prevent such a junction spiking, a barrier metal layer interposed between the aluminum layer and the source/drain region has been used to suppress the reaction of aluminum atoms of the aluminum layer with silicon atoms of the source/drain region. The barrier metal layer is formed on the entire surface of the resultant structure where the contact holes are formed. Therefore, it is practically impossible to selectively form the metal interconnections only in the contact hole by the selective CVD process since a blanket barrier metal is present on the entire surface of the semiconductor substrate.
To solve the above problems, the present invention provides a method for forming a metal interconnection capable of selectively forming a metal layer for interconnection uniformly in a contact hole or a groove.
Another objective of the present invention is to provide a contact structure fabricated by the metal interconnection forming method.
According to one embodiment of the present invention for achieving the above objective, an interdielectric layer is formed on a semiconductor substrate. Then, a predetermined region of the interdielectric layer is etched, to form an interdielectric layer pattern having a recessed region. Here, the recessed region may be a contact hole for exposing the predetermined region of the semiconductor substrate or a groove which is shallower than the thickness of the interdielectric layer. The contact hole may be a metal contact hole or a via hole used in a multi-layered metal interconnection technology. When the recessed region is a groove, the metal interconnection is formed through a damascene process. Subsequently, a barrier metal layer, i.e., a titanium nitride (TiN) layer, is formed on the entire surface of the resultant structure where the interdielectric layer pattern is formed. Here, when the recessed region is the metal contact hole for exposing the predetermined region of the semiconductor substrate, i.e., a source/drain region of a transistor, an ohmic metal layer must be formed on the entire surface of the resultant structure where the interdielectric layer pattern is formed, before forming the barrier metal layer. Then, the barrier metal layer is annealed at a predetermined temperature if necessary, to fill the grain boundary region of the barrier metal layer with oxygen atoms. This is for preventing the diffusion of silicon atoms of the semiconductor substrate through the barrier metal layer. Subsequently, an anti-nucleation layer, e.g., an insulating layer, is selectively formed only on the barrier metal layer formed on the non-recessed region, to thereby expose only the barrier metal layer formed on the sidewalls and the bottom of the recessed region. The insulating layer is for selectively forming a metal interconnection only in the recessed region in a process to be performed later. That is, using a characteristic in which the metal layer is not deposited on the insulating layer, the metal layer used for the metal interconnection is formed by the CVD process. Preferably, the insulating layer is one selected from the group consisting of a metal oxide layer, a metal nitride layer, a SiC layer, a BN layer, a SiN layer, a TaSiO layer and a TiSiO layer.
The metal oxide layer can be formed by selectively forming a layer having excellent oxidation characteristics, i.e., a metal layer, only on the barrier metal layer formed on the non-recessed region, and then exposing the metal layer to air or to O2 plasma. Also, the metal oxide layer can be formed by loading and oxidizing the resultant structure in a furnace, where the metal layer has excellent oxidation characteristics. Furthermore, the metal oxide layer can be formed by spontaneously oxidizing the resultant structure having a metal layer having excellent oxidation characteristics in a space having a predetermined degree of vacuum. The metal nitride layer, e.g., an aluminum nitride layer, may be formed by selectively forming an aluminum layer only on the barrier metal layer formed on the non-recessed region, and then exposing the aluminum layer to N2 or NH3 plasma or performing RTP in an atmosphere of NH3 and/or N2.
Alternatively, the anti-nucleation layer, i.e., the metal oxide layer, may be formed by forming a metal layer exposing the barrier metal layer in the metal contact hole on the resultant structure having the barrier metal layer and then annealing the resultant structure having the metal layer. Here, the annealing process is the same as that performed directly after forming the barrier metal layer. Therefore, an oxygen stuffing process performed directly after forming the barrier metal layer can be omitted. Here, the barrier metal layer and the metal layer exposing the barrier metal layer in the contact hole are preferably in-situ formed.
Preferably, a metal layer for forming the metal oxide layer is an Al layer, a Cu layer, a Au layer, a Ag layer, a W layer, a Mo layer, a Ta layer, a Zr layer, a Sr layer, a Mg layer, a Ba layer, a Ca layer, a Ce layer, a Y layer, a Cr layer, a Co layer, a Ni layer or a Ti layer. Also, the metal layer may be a metal alloy film containing one selected from the group consisting of Al, Au, Ag, W, Mo and Ta, and at least one selected from the group consisting of Cu, Si, Ge, Ti and Mg.
The metal layer may be formed through sputtering, a chemical vapor deposition (CVD) or a plating process. Preferably, the CVD process is performed at a temperature range corresponding to a mass transported region instead of a surface reaction limited region and at a pressure of 5 Torr or higher so that the metal layer is not formed in the recessed region. It is preferable that an argon gas and a hydrogen gas are used for a carrier gas and a reducing gas, respectively. The hydrogen gas may be used as a carrier gas. Also, the sputtering process for forming the metal layer is performed such that atoms sputtered from the target lose directionality to prevent the anti-nucleation layer from being formed in the recessed region. That is, it is preferable that the sputtering process for forming the anti-nucleation layer is performed at several mTorr using a DC magnetron sputtering apparatus without a collimator to utilize the poor step-coverage.
Alternatively, the anti-nucleation layer may be formed through a reactive sputtering process. The metal oxide layer may be formed through a O2 reactive sputtering process, and the metal nitride layer, i.e., an aluminum nitride layer, may be formed through a N2 reactive sputtering process.
As described above, the anti-nucleation layer for exposing the barrier metal layer formed in the recessed region has characteristics of the insulating layer, so that a metal layer, i.e., an aluminum layer or a copper layer may be selectively formed in the recessed region. This is because the time required for forming metal nuclei on the anti-nucleation layer being an insulating layer is several tens through several hundreds times longer than the time required for forming metal nuclei on the barrier metal layer being a metal layer. Subsequently, a metal plug for filling a region surrounded by the exposed barrier metal layer, e.g., an aluminum plug, is formed through a selective MOCVD process. The metal plug may be formed of Cu or W instead of Al. Preferably, the aluminum plug is formed through a selective MOCVD process using a precursor containing Al. It is also preferable that the selective MOCVD process for forming the aluminum plug is performed at a temperature corresponding to a surface reaction limited region of aluminum, e.g., at a temperature lower than 300xc2x0 C. It is preferable that the precursor containing the aluminum is one selected from the group consisting of tri-methyl aluminum ((CH3)3Al), tri-ethyl aluminum ((C2H5)3Al), tri-iso butyl aluminum (((CH3)2CHCH2)3Al), di-methyl aluminum hydride ((CH3)2AlH), di-methyl ethyl amine alane ((CH3)2C2H5N:AlH3), alkyl pyrroridine alane (R(C4H8)N:AlH3) and tri-tertiary butyl aluminum ((((CH3)3C)3)Al). Here, R in the alkyl pyrroridine alane (R(C4H8)N:AlH3) represents hydrogen or an alkyl of CnH2n+1. In particular, when R is methyl (CH3), the alkyl pyrroridine alane may be methyl pyrroridine alane (MPA). The alkyl pyrroridine alane is a very stable precursor compared to the di-methyl ethyl amine alane. In more detail, the bonding force between Al and N atoms in the alkyl pyrroridine alane is stronger than that between Al and N atoms in di-methyl ethyl amine alane. Since the alkyl pyrroridine alane is easily kept at room temperature compared to the di-methyl ethyl amine alane, the processing reproducibility thereof is excellent. Also, the selective MOCVD process for forming the Al plug uses an argon carrier gas and a hydrogen reducing gas.
Before forming the metal plug, a metal liner may be selectively formed on a surface of the exposed barrier metal layer. Preferably, the metal liner may be one selected from the group consisting of Al, Cu, Au, Ag, W, Mo and Ta. Also, the metal liner may be formed of a metal alloy film containing one selected from the group consisting of Al, Ag, Au, W, Mo and Ta, and at least one selected from the group consisting of Cu, Si, Ge, Ti and Mg. It is preferable that the metal liner, e.g., a Cu liner is formed by a selective CVD process, e.g., selective MOCVD process. The selective MOCVD process for forming the Cu liner is performed using a metal source containing Cu, e.g., Cu+1(hfac)TMVS. When the Cu liner is formed, the metal plug and Cu liner are mixed during an annealing process, to thereby form a metal interconnection containing copper. Accordingly, the reliability of the metal interconnection, i.e., an electromigration characteristic thereof is improved.
When the metal plug, i.e., the aluminum plug overgrows, a sharp protrusion may be formed on a surface of the metal plug. This is because the aluminum layer has a face centered cubic (FCC) structure. Accordingly, when the metal plug overgrows, it is preferable that the metal plug is planarized through a sputter etch process or a chemical mechanical polishing (CMP) process. The above-described process is of a process of forming a damascene interconnection. If necessary, the metal interconnection may be formed by additionally forming a metal layer for covering the planarized metal plug, i.e., an aluminum layer, a tungsten layer, a copper layer or an aluminum alloy layer.
According to another embodiment of the present invention for accomplishing the above object, an interdielectric layer pattern having a recessed region, a barrier metal layer pattern and an anti-nucleation layer are formed in the same manner as the first embodiment, thereby exposing the barrier metal layer formed on the sidewalls and bottom of the recessed region. Also, like the first embodiment, an ohmic metal layer may be formed on the entire surface of the resultant structure where the interdielectric layer pattern is formed, before forming the barrier metal layer, and the barrier metal layer may be annealed after forming the barrier metal layer. Then, the metal liner is selectively formed on a surface of the exposed barrier metal layer. Here, the metal liner may be a single metal liner or a double metal liner obtained by sequentially forming first and second metal liners. It is preferable that the single metal liner is a metal layer formed of one selected from the group consisting of Cu, Al, Ag, Au, W, Mo and Ta. Also, the single metal liner may be a metal alloy layer containing one selected from the group consisting of Al, Au, Ag, W, Mo and Ta, and at least one selected from the group consisting of Cu, Si, Ge, Ti and Mg. It is preferable that the first and second metal liners of the double metal liner are a copper liner and an aluminum liner, respectively. The copper liner is formed through a selective MOCVD process using a precursor containing Cu, e.g., Cu+1(hfac)TMVS, as a metal source, and the aluminum liner is formed through a selective MOCVD using a precursor containing Al as a metal source. Here, the copper liner and the aluminum liner are formed at temperature ranges corresponding to surface reaction limited regions of Cu and Al, respectively. Preferably, the precursor containing Al is one selected from the group consisting of tri-methyl aluminum ((CH3)3Al), tri-ethyl aluminum ((C2H5)3Al), tri-iso butyl aluminum (((CH3)2CHCH2)3Al), di-methyl aluminum hydride ((CH3)2AlH), di-methyl ethyl amine alane ((CH3)2C2H5N:AlH3), alkyl pyrroridine alane (R(C4H8)N:AlH3) and tri-tertiary butyl aluminum ((((CH3)3C)3)Al).
Subsequently, a metal layer, e.g., an aluminum layer, a W layer, a Cu layer or an Al alloy layer, is formed on the resultant structure where the metal liner is formed, through a combination of CVD and sputtering process. Then, the metal layer is reflowed at 350xcx9c500xc2x0 C. to form a planarized metal layer for completely filling the region surrounded by the metal liner. At this time, the planarized metal layer is changed to a metal alloy layer in which the metal liner, e.g., the Cu liner and the metal layer are mixed during the reflow process. Accordingly, the reliability of the metal interconnection, i.e., an electromigration characteristic, may be improved.
In the above-described embodiments, if the contact hole is a via hole exposing a lower metal interconnection, at least one of a wetting layer and a barrier metal layer is formed over the entire surface of the semiconductor substrate having the via hole. Subsequently, an anti-nucleation layer exposing the inside of the via hole is formed on the semiconductor substrate where at least one of a wetting layer and a barrier metal layer has been formed, and an upper metal interconnection filling the inside of the exposed via hole is formed. Here, in the case where the lower metal interconnection is formed of W and the upper metal interconnection is formed of Al or Al alloy, the barrier metal layer is necessarily formed. This is because contact failure such as an increase in via resistance occurs when the W layer and the Al layer react with each other. The wetting layer is preferably formed of Ti or Ta. The upper metal interconnection is formed by forming a metal liner and/or a metal plug in the same manner as either of the above-described embodiments of the present invention, forming a metal layer such as an Al layer or an Al alloy layer on the entire surface of the resultant structure by a physical vapor deposition (PVD) process, and reflowing the resultant structure having the metal layer.
To achieve another objective, the present invention provides a contact structure including a first conductive layer formed on a semiconductor substrate, an interdielectric layer pattern which is formed over the entire surface of the semiconductor substrate having the first conductive layer and which exposes a predetermined region of the first conductive layer, an anti-nucleation layer which is formed on the top surface of the interdielectric layer pattern and which exposes the contact hole, and a second conductive layer which is formed on the anti-nucleation layer and which fills the contact hole.
The anti-nucleation layer is an insulator layer such as an oxide layer or a nitride layer. The oxide layer may be a metal oxide layer or a silicon oxide layer, and the nitride layer may be a metal nitride layer or a silicon nitride layer. The metal oxide layer is a material layer produced by oxidizing a metal layer having excellent oxidation characteristics, for example, an Al oxide layer, a titanium oxide layer, a tantalum oxide layer, a zirconium oxide layer, a chrome oxide layer, a cobalt oxide layer or a nickel oxide layer. Also, the metal nitride layer may be an insulator layer such as an Al nitride layer.
A conductive layer may be further provided between the anti-nucleation layer and the interdielectric layer pattern. The conductive layer is a partially remaining metal layer for forming the anti-nucleation layer, and may be an Al layer, a Ti layer, a Ta layer, a Y layer, a Zr layer, a Cr layer, a Co layer or a Ni layer.
In the case where the first conductive layer is a lower metal interconnection formed of metal such as Al, Al alloy or W, the contact hole is a via hole. Here, a conformal metal layer is interposed between both the anti-nucleation layer and the interdielectric layer pattern and between the bottom and side walls of the contact hole and the second conductive layer. The conformal metal layer may have a structure in which the wetting layer and the barrier metal layer are sequentially stacked, or may be a single metal layer consisting of either the wetting layer or the barrier metal layer. In the case where the contact hole is a via hole, both the first and second conductive layers may be copper layers. Here, the conformal metal layer preferably includes at least a barrier metal layer. This is because copper atoms contained in the copper layer are susceptible to diffusion into the interdielectric layer pattern when the copper layer contacts the interdielectric layer pattern.
Also, in the case where the first conductive layer is an impurity layer, a doped polysilicon layer or a refractory metal silicide layer, the contact hole may be a metal contact hole. In this case, a conformal metal layer is interposed between both the anti-nucleation layer and the interdielectric layer pattern and between the bottom and sidewalls of the contact hole and the second conductive layer. The conformal metal layer has a structure in which an ohmic metal layer and a barrier metal layer are sequentially stacked. In the case where the contact hole is a metal contact hole, the second conductive layer may be a copper layer. Here, the conformal metal layer preferably includes at least a barrier metal layer.
According to the present invention, the anti-nucleation layer is selectively formed only on the barrier metal layer formed on the non-recessed region, thereby selectively forming the metal plug or the metal liner in the recessed region and further form the metal interconnection for completely filling a contact hole and a groove having a high aspect ratio.